Interface IP Cores for Samsung

Compare 139 Interface IP Cores for Samsung from 9 vendors (1 - 10)

DP and eDP TX/RX PHY IP
- eDP v1.5 compliant
- Supports for 1.62Gbps to Max 8.1Gbps data rate
- PSR, PSR2 supported for low power consumption ( FW_SLEEP, FW_STANDBY supported )
- Supports for eDP v1.5 feature such as AUX-less Link Training
MIPI C/D-PHY Combo IP
- Compliant to MIPI D-PHY v3.0, C-PHY v2.1 specification
- Area efficient macro optimized for placement for dense SoC designs
- Support Uni-(TX or RX) and Bi-directional(TX and RX) mode
- Support emphasis architecture over lossy channel for TX
- Support equalize architecture over lossy channel for RX
20G MSS (Multi-standard SerDes) PHY
- Developing under SF4X CMOS technology (2025.06.30 MTO)
- Compliant to multiple standards, max datarate 20Gb/s
- Channel Configuration for Data Lanes: 1, 2 or 4 Data Lanes
- Reliable Ring OSC PLL based architecture for Low power consumption
PCIe Gen4.0 PHY IP
- Best-in-class Power / Performance / Area competitiveness
- Compliant to PCIe 4.0 Base specification
- Supports lane configurations according to the user’s demands
- Supports data rates of 2.5GT/s, 5.0GT/s, 8.0GT/s and 16GT/s
PCIe Gen5/6 PHY IP
- Best-in-class Power / Performance / Area competitiveness
- Compliant to PCIe 5.0/6.x Base specification
- Supports lane configurations according to the customer’s demands
- Supports data rates of 2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32GT/s and 64GT/s (PAM4)
USB4 PHY - SS SF4X, North/South Poly Orientation
- Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
- Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
- x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
- Low active and standby power
PHY for PCIe 6.0 and CXL
- Architecture optimized for HPC, AI/ML, storage, and networking
- Ultra-long reach, low latency, and low power
- Advanced DSP delivers unmatched performance and reliability
- Comprehensive real-time diagnostic, monitor, and test features
- Bifurcation support for x1, x2, x4, x8, and x16 lanes
PHY for PCIe 4.0 - Low-power, long-reach, multi-protocol PHY for PCIe 4.0
- Wide range of protocols that support networking, high-performance computing (HPC), and applications
- Low-latency, long-reach, and low-power modes
- Multi-Link PHY—mix protocols within the same macro
- EyeSurf —non-destructive on-chip oscilloscope
- User-friendly graphical interface provides easy access to embedded bit-error-rate (BER) and pattern testers and monitors to measure the link performance in real time
USB 2.0 femtoPHY SS SF5A 18 x1, OTG, North/South (vertical) poly orientation
- Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
- Supports the USB 2.0 protocol and data rate (480 Mbps)
- Supports the USB Type-C specification
- USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
USB 2.0 femtoPHY - SS SF5A 18 x1, OTG, North/South (vertical) poly orientation
- Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
- Supports the USB 2.0 protocol and data rate (480 Mbps)
- Supports the USB Type-C specification
- USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design

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