PCIe 4/3/2 SerDes PHY - Samsung 14nm

Overview

Key Features

• Duplex lane configurations of x2, x4, and x35
• Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
• Support for AC-coupled interfaces
• Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
• BER of 10-15 for CEI11-LR/SR and BER of 10-12 for SFI, XFI, PCIe and Gbe protocols
• A wide range of PLL multiplication supporting low reference clock frequencies
• Tight skew control of 2UI between lanes of the PMA
• Built-in Self Test (BIST) with ATPG and AC/DC boundary scan support
• Built-in PRBS pattern generation and checking for standalone loopback testing
• Continuous time linear equalizer (CTLe) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies

Deliverables

• PMA Hard Macro
• PCS-BIST Soft Macro
• Datasheet
• SoC integration guide
• Optional design integration and bring-up support services

Technical Specifications