The 16G Multi-Link and Multi-Protocol PHY is a silicon-proven, high-end SerDes operating at speeds from 1.25Gbps to 16Gbps featuring long-reach equalization capability at very low active and standby power. This SerDes offers ultra-low exit latency for time-critical applications. It simultaneously supports PCI Express® (PCIe®) 4.0, 10G-KR, and QSGMII/SGMII, and other protocols allowing great flexibility to mix and match protocols within the same macro.
PHY for PCIe 4.0 - Low-power, long-reach, multi-protocol PHY for PCIe 4.0
Overview
Key Features
- Wide range of protocols that support networking, high-performance computing (HPC), and applications
- Low-latency, long-reach, and low-power modes
- Multi-Link PHY—mix protocols within the same macro
- EyeSurf —non-destructive on-chip oscilloscope
- User-friendly graphical interface provides easy access to embedded bit-error-rate (BER) and pattern testers and monitors to measure the link performance in real time
- Extensive set of isolation, test modes, and loop-backs including APB and JTAG
- Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces
- Selectable serial pin polarity reversal for both transmit and receive paths
Benefits
- High Performance: Single macro supports max 16Gbps with up to 16 lanes for long-reach applications
- Mature and Silicon Proven: Compliance proven, customer SoCs in volume production
- Low Risk: Fully validated by Cadence’s rigorous IP qualification process and system stress tests
- Ease of Use: Fully verified pre-integrated IP delivery, with package and signal integrity support and firmware for rapid bring-up
Block Diagram
Deliverables
- PMA Hard Macro
- PCS-BIST Soft Macro
- Datasheet
- SoC integration guide
- Optional design integration and bring-up support services
Technical Specifications
Maturity
In Production
Samsung
In Production:
14nm