Memory & Libraries IP for GLOBALFOUNDRIES

Welcome to the ultimate Memory & Libraries IP for GLOBALFOUNDRIES hub! Explore our vast directory of Memory & Libraries IP for GLOBALFOUNDRIES
All offers in Memory & Libraries IP for GLOBALFOUNDRIES
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Compare 113 Memory & Libraries IP for GLOBALFOUNDRIES from 20 vendors (1 - 10)
  • 5V ESD Clamp in GlobalFoundries 180nm LPe
    • A GlobalFoundries 180nm LPe Specialized 5V ESD Clamp.
    • A key attribute of this 5V Clamp is that it can be used for either signal protection or 1.8V power supplies.
    • The clamp is a single cell, 44um x 32um in size. It is built from the substrate to metal 6.
    Block Diagram -- 5V ESD Clamp in GlobalFoundries 180nm LPe
  • 1.8V and 3.3V Radiation-Hardened GPIO with Optimized LDO in GF 12nm
    • A radiation-hardened GlobalFoundries 12nm LP/LP+ Flip-Chip IO library with both 1.8V and 3.3V GPIO, fail-safe GPI, analog cell, and associated ESD. Also features an LDO optimized for use with 3.3V GPIO.
    • This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function.
    Block Diagram -- 1.8V and 3.3V Radiation-Hardened GPIO with Optimized LDO in GF 12nm
  • 3.3V I/O Library with I2C compliant ODIO IN GF 65/55nm
    • A 3.3V wire-bond I/O library, a 1.2V ODIO and 5V tolerant ODIO.
    • This library is a production-quality, silicon-proven I/O library in GlobalFoundries 65/55nm technology.
    • The library offers a 3.3V GPIO with two selectable inputs, slew rate control, and an optional active tri-state, as well as a GPIO with an ultra-wide supply range and an optional glitch filter.
    Block Diagram -- 3.3V I/O Library with I2C compliant ODIO IN GF 65/55nm
  • 1.5V to 3.3V GPIO with Tri-State Output Driver in GF 180nm
    • A GlobalFoundries 180nm BCD Lite Wirebond GPIO library with tri-state out- put driver, schmitt trigger receiver and associated ESD.
    • This silicon-proven, wirebond library in GlobalFoundries 180nm BCD lite is a specialty I/O similar to Soundwire.
    • Featuring a 1.5V to 3.3V GPIO, as well as a tri-state output driver, an analog test point switch, and 7V OTP mode.
    Block Diagram -- 1.5V to 3.3V GPIO with Tri-State Output Driver in GF 180nm
  • GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
    • The 2.5Gbps LVDS transceiver in GlobalFoundries LP/LP+ is designed for high-speed, low-power data transmission in radiation-intensive environments.
    • Engineered with a Rad-Hard by Design approach, the Rad-Hard cells have been proton tested to 64 MeV with a flux exceeding 1.3E+09, and is latch-up proven to 200mA across -40C to 125C, ensuring robust immunity against TID, SEE, and SEL effects.
    Block Diagram -- GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
  • GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
    • This SLVS I/O Library delivers a robust, high-performance solution for high-speed differential signaling in GlobalFoundries 12nm process technology.
    • Designed for optimal signal integrity, this 0.8V SLVS transceiver features fast rise and fall times, low propagation delay, and built-in pre-emphasis to enhance signal quality over longer traces.
    • With support for data rates up to 3Gbps, it enables reliable, low-power communication while maintaining excellent noise immunity.
    Block Diagram -- GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
  • Automotive Grade 1 – Differential Output Driver on GLOBALFOUNDRIES 22FDX-AG1
    • Differential output to chip core
    • Wide frequency range support up to 2000MHz output for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    • Low power consumption
    Block Diagram -- Automotive Grade 1 – Differential Output Driver on GLOBALFOUNDRIES 22FDX-AG1
  • LVDS interfaces
    • Wide operating range
    • High data rates
    • Very flexible programmability
    • Excellent signal integrity
    • TIA/EIA644A LVDS and sub-LVDS compatibility
    • Receiver also compatible with LVPECL
    Block Diagram -- LVDS interfaces
  • 1KByte EEPROM IP with configuration 66p16w8bit
    • Global Foundries Embedded EEPROM 0.13 um
    • 1056 Byte of available memory 8(bit per word) x 16(words per page) x 66(pages) bit
    • High density of memory cells
    • Writing and erasing data by one high-voltage pulse
    Block Diagram -- 1KByte EEPROM IP with configuration 66p16w8bit
  • 2048bits EEPROM with configuration 16p8w16bit
    • GlobalFoundries Embedded EEPROM 0.13 um
    • 2048bit of available memory 16(bit per word) × 8(words per page) × 16(pages) bit
    Block Diagram -- 2048bits EEPROM with configuration 16p8w16bit
×
Semiconductor IP