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Clock Synthesizer IP for GLOBALFOUNDRIES

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Compare 10 Clock Synthesizer IP for GLOBALFOUNDRIES from 4 vendors (1 - 10)
  • ULP Clock-Generator - GLOBALFOUNDRIES 22FDX
    • ABB-enabled, All-Digital PLL clock generator for ultra-low power clocking in highly energy efficient Systems on Chip
    • The Ultra-Low Voltage Clock Generator is targeted at Systems on Chip (SoCs) employing advanced power management techniques.
    • The robust, fully digital architecture allows operation in a wide voltage and frequency range. Unique fast lock and instant frequency change features maximize the energy efficiency of the targeted systems.
    Block Diagram -- ULP Clock-Generator - GLOBALFOUNDRIES 22FDX
  • ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX
    • The All Digital Frequency Locked Loop (ADFLL) architecture is reduced to the minimum amount of hardware necessary to generate a 10 MHz clock
    • High energy efficiency: Only 5 μW are consumed during operation
    • A reference clock divider allows reference clock frequencies from 32 kHz to 1 MHz
    Block Diagram -- ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX
  • Low Voltage, Low Power Fractional-N PLL
    • GlobalFoundries GF22FDX
    • Small size (< 0.005 sq mm)
    • Low Power (< 0.7mW)
    Block Diagram -- Low Voltage, Low Power Fractional-N PLL
  • Low Voltage, Low Power Fractional-N PLLs
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    Block Diagram -- Low Voltage, Low Power Fractional-N PLLs
  • Fractional-N PLLs for Performance Computing
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLLs for Performance Computing
  • Fractional-N PLL for Performance Computing in GlobalFoundries 12LPP/14LPP
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.004 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLL for Performance Computing in GlobalFoundries 12LPP/14LPP
  • Fractional-N PLL for Performance Computing in GlobalFoundries 22FDX
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLL for Performance Computing in GlobalFoundries 22FDX
  • General Purpose Fractional-N PLLs
    • Low power, suitable for logic clocking applications
    • Extremely small die area, using a ring oscillator
    • Twelve bits fractional resolution
    Block Diagram -- General Purpose Fractional-N PLLs
  • Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter
    • 3GPP superset LO sub-system (All bands + CA)
    • PLL1 [0.49mm2] for LTE with VCO1
    • PLL2 [0.76mm2] for LTE&GSM with VCO1 and VCO2
    • Small size, high-performance and low-power (24mW)
    Block Diagram -- Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter
  • Low noise from 8GHz to 11.3GHz differential LC VCO
    • Phase noise -108dB typical
    • Single 1.2V Power Supply
    • VCO center frequencies 8.5GHz, 10.0GHz, 10.7GHz, 11.1GHz
    • Each VCO frequency tuning ±8%
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