ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX

Overview

Key Features

• The All Digital Frequency Locked Loop (ADFLL) architecture is reduced to the minimum amount of hardware necessary to generate a 10 MHz clock
• High energy efficiency: Only 5 μW are consumed during operation
• A reference clock divider allows reference clock frequencies from 32 kHz to 1 MHz

Block Diagram

Deliverables

• Verilog simulation models
• .lib/.db timing and power models (NLDM)
• .lef layout abstract views
• Milkyway database
• GDSII files
• LVS netlist

Technical Specifications