ADC / DAC IP for GLOBALFOUNDRIES
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12-bit, 4 GSPS High Performance IQ ADC in GF22FDX
- GF22FDX Process
- 12-bit resolution, 4GSPS update rate
- Dual ADC configured as IQ Pair
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12 bit, 500 MSPS ADC on GF 22FDX
- The ODT-ADS-12B500M-G22FDX is an ultra-low power ADC designed in a 22nm CMOS process.
- This 12-bit, 500MSPS ADC supports input signals up to 100MHz and features a differential full-scale range of 0.8Vpp and excellent static and dynamic performance.
- The ADC architecture is optimized to maximize performance while minimizing power and area consumption. The ADC includes an integrated input buffer.
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12-bit, 2 GSPS High Performance ADC in 12nm CMOS
- The ODT-ADS-12B2G-12nm is an ultra-highperformance time-interleaved ADC designed in a 12nm CMOS process.
- This 12-bit, 2GSPS ADC supports input signals up to 1.0 GHz and features a differential full-scale range of 0.8Vpp and excellent static and dynamic performance.
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10-bit, 5 MSPS ADC in 12nm CMOS on GF 12nm LP+
- The ADC is an ultra-low-power ADC designed in a GF 12nm LP+ process.
- This 10-bit, 5MSPS ADC supports input signals up to 1 MHz and features 2V differential full-scale input range with excellent static and dynamic performance. The input front-end includes a 4:1 mux.
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Current Steering 6-bit RF DAC on TSMC, 28nm
- 6-bit resolution
- 1GSPS update rate.
- Differential 5mA current (sink) output
- Functional from -40°C to 125°C
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6-bit, 5 GSPS DAC - GlobalFoundries, 22FDX
- The D6B5G is ultra-low power, high-speed digital to analog converter (DAC) intellectual property (IP) block.
- It has a 6-bit resolution, and a sampling speed of 5 gigasamples per second (GSPS).
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12-bit, 10 GSPS DAC - GlobalFoundries GF22FDX
- The D12B10G is an ultra-low power, high-speed digital to analog converter (DAC) intellectual property (IP) block.
- It is a 12-bit current steering DAC with maximum sampling rate of 10 gigasamples-per-second (GSPS).
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11-bit, 5 GSPS SAR ADC - GlobalFoundries GF22FDX
- The A11B5G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block.
- It is a hybrid-SAR ADC, with 11-bit resolution and a sampling rate of 5 gigasamples-per-second (GSPS).
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12-bit 40nm 1.1V 64MHz-to-340MHz continuous-time Delta-Sigma ADC
- Integrated Dual-Channel Continuous-time Delta-Sigma Modulator (I + Q)
- Integrated Dual decimate-by-8 Cascaded-Integrator-Comb Decimation Filter
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11 Bit 100 kS/s Ultra-Low Power SAR ADC on GlobalFoundries 22FDSOI
- The ADC IP is a general-purpose successive approximation converter for low-power medium resolution applications. Sample rate, resolution and power consumption are configurable.
- It is built using typical differential capacitor-DAC architecture, clocked comparator and bootstrapped switches. No additional reference voltage is required, achieving lmost rail-to-rail input. The target applications are environmental and biomedical signal processing.
