ADC / DAC IP for GLOBALFOUNDRIES

The D6B5G is ultra-low power, high-speed digital to analog converter (DAC) intellectual property (IP) block.
It has a 6-bit resolution, and a sampling speed of 5 gigasamples per second (GSPS).

The D12B10G is an ultra-low power, high-speed digital to analog converter (DAC) intellectual property (IP) block.
It is a 12-bit current steering DAC with maximum sampling rate of 10 gigasamples-per-second (GSPS).

The A11B5G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block.
It is a hybrid-SAR ADC, with 11-bit resolution and a sampling rate of 5 gigasamples-per-second (GSPS).

The ADC IP is a general-purpose successive approximation converter for low-power medium resolution applications. Sample rate, resolution and power consumption are configurable.
It is built using typical differential capacitor-DAC architecture, clocked comparator and bootstrapped switches. No additional reference voltage is required, achieving lmost rail-to-rail input. The target applications are environmental and biomedical signal processing.

The WEA10IDA45 is a 10-bit current DAC
It accepts a current input of 4 uA and is capable of sinking and sourcing current up to 4 mA The DAC output has 1023 sink and 1023 source settings that is programmed using a parallel 10-bit digital bus
The current DAC output can be switched to high impedance state
The iDAC operates from a power supply ranging from 1.8 V to 3.0 V

The WEAADC12BHSI22G is a 12-bit time interleaved Successive Approximation Analog-toDigital Converter (ADC) that supports both singleended and differential operation, depending on the input and reference connections
It integrates 13 WEAADC12BHS22G with programmable clock skew (50ps coarse 4ps fine with minimum step 0.25ps) and pre/post-calibration logic on each
Operating on a 0.8 V power supply, the WEAADC12BHSI22G can provide output up to 2GSPS in 13-interleaved mode
The ADC can be clocked with 2GHz clock

The WEAADC12BHS22G is a 12-bit Successive Approximation Analog-to-Digital Converter (ADC) that supports both single-ended and differential operation, depending on the input and reference connections
It integrates a split-capacitor DAC with a built-in track-and-hold circuit, a dynamic comparator with DC-offset autocalibration, SAR logic state machine, and pre/post-calibration logic
The device also includes gain and offset calibration mechanisms
Operating on a 0.8 V power supply, the WEAADC12BHS22G requires 13 clock cycles for conversion, in 12-bit resolution mode, with digital data available at the rising edge of the 14th clock pulse