ADC / DAC IP for GLOBALFOUNDRIES
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ADC / DAC IP
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82
ADC / DAC IP
for GLOBALFOUNDRIES
from 16 vendors
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24-bit Cap-less ADC 104.5 dB SNR low power and low latency 4 channels
- I2C and APB control interface
- Embedded low noise voltage regulator for best resilience to power supply noise
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6-bit, 1 GSPS High Performance DAC in 28nm CMOS
- 6-bit resolution, update rate up to 1 GSPS
- Fully differential current output, fully specified from -40C to 125C
- Ultra low power dissipation
- Wide output bandwidth
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12-bit 40nm 1.1V 64MHz-to-340MHz continuous-time Delta-Sigma ADC
- Integrated Dual-Channel Continuous-time Delta-Sigma Modulator (I + Q)
- Integrated Dual decimate-by-8 Cascaded-Integrator-Comb Decimation Filter
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12-bit, 10 GSPS DAC - GlobalFoundries GF22FDX
- The D12B10G is an ultra-low power, high-speed digital to analog converter (DAC) intellectual property (IP) block.
- It is a 12-bit current steering DAC with maximum sampling rate of 10 gigasamples-per-second (GSPS).
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12-bit, 10 GSPS ADC - GlobalFoundries GF22FDX
- 12-bit resolution
- 10 GSPS sampling rate
- 6 GHz Input Bandwidth
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6-bit, 5 GSPS DAC - GlobalFoundries, 22FDX
- The D6B5G is ultra-low power, high-speed digital to analog converter (DAC) intellectual property (IP) block.
- It has a 6-bit resolution, and a sampling speed of 5 gigasamples per second (GSPS).
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16-bit Sigma Delta ADC
- Globalfoundries 130LP
- Silicon proven
- Low power
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11-bit, 5 GSPS SAR ADC - GlobalFoundries GF22FDX
- The A11B5G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block.
- It is a hybrid-SAR ADC, with 11-bit resolution and a sampling rate of 5 gigasamples-per-second (GSPS).
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8/10-bit Digital-to-Analog Converter
- The agileDAC GP is a digital-to-analog converter that uses a traditional capacitive DAC architecture.
- The agileDAC uses its own internal reference voltage.
- The architecture can achieve up to 10-bit resolution at sample rates up to 16 Msps.
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12-bit Analog-to-Digital Converter
- The agileADC 12 Analog-to-Digital Converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 12-bit resolution at sample rates up to 64 MSPS. It includes a 16-channel input multiplexor that can be configured to be buffered or unbuffered, and support differential or single-ended inputs.
