Wide band 3.5 GHz -7 GHz low noise PLL synthesizer

Overview

055TSMC_PLL_02 is a PLL frequency synthesizer that generates a high-frequency signal in the range from 3.5GHz to 7GHz. The synthesizer consists of 4 voltage-controlled oscillators (VCO) with internal LC circuit and automatic subband selection system; a digital phase-frequency detector (PFD); a precision charge pump (CP) with integrated adjustable loop filter; a programmable divider of reference signal and a system of programmable feedback dividers controlled by a delta-sigma modulator (DSM)

Key Features

  • TSMC CMOS 55 nm
  • Output frequency range from 3.5 MHz to 7 GHz
  • Reference frequency range from 5 MHz to 50 MHz
  • Low jitters (350fs)

Block Diagram

Wide band 3.5 GHz -7 GHz low noise PLL synthesizer Block Diagram

Applications

  • Frequency clock generation

Deliverables

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Technical Specifications

Foundry, Node
TSMC CMOS 55 nm
Maturity
Silicon proven
Availability
Now
TSMC
Pre-Silicon: 55nm G
Silicon Proven: 55nm FL
×
Semiconductor IP