VeriSilicon SMIC 0.13¦Ìm 1.2V/3.3V DUPIO_01 Library

Overview

Key Features

• SMIC 0.13¦Ìm Logic 1P8M Salicide 1.2V/3.3V process
• Low area and low cost design using DUP technique
• 1.2V core power, 3.3V IO, digital IO supports 5V tolerance
• This library includes analog I/O cell part
• Configurable output driving capability with different slew rate
• Supports configurable pull up and pull down resistor
• Supports both CMOS input and Schmitt input with LVTTL compatible
• Provides 2Mhz ~ 27Mhz OSC IO cell
• Suitable for six, seven, or eight metal layers of physical design
• Competitive pad pitch and height
• More detail, please go to below website to contact VeriSilicon location sales:http://www.verisilicon.com/cn/contactus.asp

Benefits

• Databook in electronic form
• Verilog models and Synopsys synthesis models
• Cadence Silicon Ensemble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist

Technical Specifications