The Tessent Embedded Analytics Bus Monitor provides non-intrusive monitoring of interconnect activity across all major standards, including Arm® AMBA® AXI, ACE, and ACE-lite.
The Bus Monitor enables full transaction-level visibility of traffic buses with a wide range of measurements, analytics and statistics gathering. All of these are run-time configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering. The modules can track transactions (e.g. trace) and automatically gather statistics to identify issues such as contention, peak traffic, and deadlock.
All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.
Tessent Bus Monitor
Overview
Key Features
- Full transaction and trace-level visibility of on-chip bus traffic
- Wide range of measurements, analytics statistics: Transactions, Bus cycles, latency, duration, beats, bus concurrency
- Supports AXI, ACE, ACE-lite
- Run-time configurable
- Logic analyzer style controls and dependencies
Benefits
- Accelerate SoC debug and SW development
- Identify and resolve hard-to-identify bugs significantly faster compared to traditional software-only solutions
- Root-cause performance degradations and memory corruption
- Better visibility and analytics
- Integrated part of the Tessent Embedded Analytics whole system solution
Block Diagram
Deliverables
- Parameterized soft core (Verilog RTL)
- Available UVM verification IP
- Optional Tessent SystemInsight IDE software
- Optional Tessent Embedded SDK software development kit
Technical Specifications
Maturity
In silicon
Availability
Now