SSTL_15 IO Pad Set
Overview
The SSTL_15 library supports bidirectional single-ended and differential SSTL_15 signaling. The driver/receiver pairs, with embedded power cells, are supplied with a full complement of calibration, voltage reference, power, spacer, and adapter cells to assemble a pad ring by abutment. An included rail splitter allows isolated SSTL domains to be placed in the same pad ring with other power domains while maintaining continuous VDD/VSS in the pad ring for robust ESD protection.
Key Features
- Full DDR3 capability - 800MHz (1600 Mbps)
- Low Power driving standard DDR3 memories
- 1.8V FETs
- Full complement of cells to build padring (20)
- Full ODT Capability:
- Either fixed 6-Bit programmation (program from core)
- Or, dynamic 6-Bit PVT calibration (external reference resistor)
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
GLOBALFOUNDRIES 28nm SLP
Maturity
Silicon Proven
Availability
Available Now