USB 3.1 PHY

Overview

USB 3.1 is the most recent version of the USB (Universal Serial Bus) standard for connecting electronic devices in host and device mode. USB 3.1 IP is targeted for integration into SoCs for media storage, and playback devices requiring faster bandwidth between PCs and portable electronic devices.

The vendor offers best-in-class SerDes IP for USB 3.1 PHY. The PHY is designed for low latency, low power, small form factor, high interface speeds for high performance computing. The PHYs comes complete with a physical media attachment (PMA) hard macro that supports USB 3.0 and USB3.1 protocols, a physical coding sublayer (PCS) and soft macro for USB that is PIPE4.2 compliant.

Key Features

  • Parallel data widths of 8bits and 16bits
  • QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
  • Support signal loss and receiver detection using programmable multi-tap & de-emphasis
  • Support 1m cable
  • High speed low jitter (0.17UI) 10GHz PLL

Deliverables

  • User and integration guides
  • Netlist
  • Timing library
  • Register map
  • Verilog
  • IBIS-AMI models
  • LEF views
  • Layout Versus Schematic (LVS)
  • Design Rule Check (DRC) reports
  • Silicon

Technical Specifications

Short description
USB 3.1 PHY
Vendor
Vendor Name
TSMC
Silicon Proven: 28nm HPC
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Semiconductor IP