PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 65nm SP process
Overview
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 65nm SP/RVT Logic process.
Technical Specifications
Foundry, Node
UMC 65nm SP
UMC
Pre-Silicon:
65nm
SP
Related IPs
- PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 40nm LP process
- PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 0.11um HS/FSG process
- PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 0.11um HS/AE process
- PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 0.13um HS/FSG process
- PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 0.13um HS/FSG process
- PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.11um HS/AE process