PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 65nm SP process
Overview
Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT Logic process.
Technical Specifications
Foundry, Node
UMC 65nm SP
UMC
Pre-Silicon:
65nm
SP
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