PCI Bus Arbiter

Key Features

• Compliant with PCI bus specification 2.2.
• Designed for ASIC and PLD implementations in various system environments.
• Fully static design with edge triggered flip-flops.
• Supports two to eight bus masters.
• Choice between rotating priority or fixed priority scheme.
• Bus parking.
• Supports both 32-bit and 64-bit PCI bus.
• Fast request-to-grant turn around time.
• Quiet cycle during master switch.
• Master time-out.

Technical Specifications