MIPI D-PHY CSI-2 TX (Transmitter) in GlobalFoundries 22FDX

Overview

The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Specification for
D-PHY v2.1, which is backward compatible with MIPI Specification for
D-PHY v1.2. The IP is configured as a MIPI master optimized for CSI-2SM
(Camera Serial Interface) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for high-Speed data traffic while low power functions are mostly used for control.

Key Features

Consists of 1 Clock lane and up to 4 Data lanes
Supports MIPI Alliance Specification for D-PHY Version 2.1
Supports both high speed and low-power modes
80 Mbps to 2.5Gbps data rate in high speed mode
10 Mbps data rate in low-power mode
Low power dissipation

Benefits

Comprehensive embedded DFT features for allowing cost-effective high-volume manufacturing tests
The D-PHY system is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow.

Block Diagram

Applications

Mobile
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

GlobalFoundries 22FDX

Maturity

Silicon Proven

Availability

Now

GLOBALFOUNDRIES

Pre-Silicon: 22nm FDX

TSMC

Silicon Proven: 40nm LP

Request Info