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MIPI D-PHY IP

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Search (28)
Compare 28 MIPI D-PHY IP from 3 vendors (1 - 10)
  • MIPI D-PHY in ON Semiconductor 180nm
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.1
    • Supports standard PHY transceiver compliant to MIPI Specification
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high speed mode with a bit rate of 80-1500 Mb/s
    Block Diagram -- MIPI D-PHY in ON Semiconductor 180nm
  • MIPI D-PHY TSMC 130nm
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.1
    • Supports standard PHY transceiver compliant to MIPI Specification
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high speed mode with a bit rate of 80-1500 Mb/s
    Block Diagram -- MIPI D-PHY TSMC 130nm
  • MIPI D-PHY V1.2@2.5GHz TSMC28nm HPC+
    • Compliant to MIPI D-PHY specification Version 1.1
    • Supports standard PHY transceiver compliant to MIPI Specification
    Block Diagram -- MIPI D-PHY V1.2@2.5GHz TSMC28nm HPC+
  • MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
    • Supports standard PHY transceiver compliant to MIPI Specification
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
    Block Diagram -- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
  • MIPI D-PHY Universal IP in TSMC 40LP for Automotive
    • Consists of 1 Clock lane and 4 Data lanes
    • Complies with MIPI Standard 1.1 for D-PHY
    • Supports both high speed and low-power modes
    Block Diagram -- MIPI D-PHY Universal IP in TSMC 40LP for Automotive
  • MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 40LP
    • Consists of 1 Clock lane and 4 Data lanes
    • Complies with MIPI Standard 1.1 for D-PHY
    • Supports both high speed and low-power modes
    Block Diagram -- MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 40LP
  • MIPI D-PHY CSI-2 RX (Receiver) in TSMC 40LP
    • Consists of 1 Clock lane and 4 Data lanes
    • Complies with MIPI Standard 1.1 for D-PHY
    • Supports both high speed and low-power modes
    • 80 Mbps to 1.5Gbps data rate in high speed mode
    Block Diagram -- MIPI D-PHY CSI-2 RX (Receiver) in TSMC 40LP
  • MIPI D-PHY Universal IP in SMIC 130nm
    • Designed for SMIC 130nm
    • Consists of 1 Clock lane and 4 Data lanes
    • Complies with MIPI Standard 1.1 for D-PHY
    Block Diagram -- MIPI D-PHY Universal IP in SMIC 130nm
  • MIPI D-PHY Universal IP in TSMC 28HPM
    • Designed for TSMC 28nm
    • Consists of 1 Clock lane and 4 Data lanes
    • Complies with MIPI Standard 1.1 for D-PHY
    Block Diagram -- MIPI D-PHY Universal IP in TSMC 28HPM
  • MIPI D-PHY NEC 90nm
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.1
    • Supports standard PHY transceiver compliant to MIPI Specification
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high speed mode with a bit rate of 80-1500 Mb/s
    Block Diagram -- MIPI D-PHY NEC 90nm
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