The MXL-CPHY-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Master supporting camera interface CSI-2 v1.3 in DPHY and CPHY modes. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP
Overview
Key Features
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI® Specification for D-PHY Version 2.1
- Supports MIPI® Specification for C-PHY Version 1.2
- One Lane in D-PHY mode
- One Lane in C-PHY mode
- Supports both high speed and low-power modes
- 80 Mbps to 1.5 Gbps data rate in high speed D-PHY mode
- 80 Msps to 1.5 Gsps data rate in high speed C-PHY mode
- 10 Mbps data rate in low-power mode
- Low power dissipation
- Testability support
- Optional resistance termination calibrator
Benefits
- Supports both C-PHY and D-PHY using same pins
- Extended data rate and higher power efficiency in C-PHY mode
Block Diagram
Applications
- Mobile
- Cameras/Sensors
- IoT
- VR/AR/MR
- Consumer electronics
- Automotive
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- IBIS Model
- Verilog Model
- Timing Model
- Integration Guidelines
- RTL
- Documentation
- One year support
Technical Specifications
Foundry, Node
TSMC, 65LP
Maturity
Silicon Proven
Availability
Now
TSMC
Pre-Silicon:
65nm
LP
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