The LVDS library provides an LVDS driver, receiver, and
temperature stable voltage reference capable of supporting 16 drivers
operating at data rates up to 2.0 Gbps. The pad set includes a full
complement of power, spacer, and adapter cells to assemble a
complete pad ring by abutment. An included rail splitter allows
isolated LVDS domains to be placed in the same pad ring with other
power domains while maintaining continuous VDD/VSS in the pad
ring for robust ESD protection.
LVDS I/O Pad Set
Overview
Key Features
- Input receive sensitivity of 75mV peak differential (without hysteresis)
- Common mode range from 0V to 2.4V (limited by Power Supply)
- Powered by 2.5V I/O and 1.1V core supplies
- Power consumption: 5 mW typ & 8.5 mW max @ 1GHz
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
SMIC 40nm
Maturity
Silicon Proven
Availability
Available Now
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