LPDDR2 / LPDDR3 / DDR3 / DDR3L / DDR3U / DDR4 Combo I/O Pad Set
Overview
The LPDDR2/3_DDR3/4 library includes the combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and a full complement of support cells for both single-ended and differential signaling for LPDDR2, LPDDR3, DDR3, DDR3L, DDR3U, and DDR4 applications. Also included is a full complement of power, corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
Key Features
- • User programmable drive strength
- o DDR3 – ZOUT = 34 / 40 ?
- o DDR4 – ZOUT = 34 / 48 ?
- o LPDDR2 – ZOUT = 34 / 40 / 48 / 60 / 80 ?
- o LPDDR3 – ZOUT = 34 / 40 ?
- • User programmable on-die termination
- o DDR3 – 120 / 60 / 40 / 30 / 24 / 20 / 17 ?
- o DDR4 – 240 / 120 / 80 / 60 / 48 / 40 / 34 ?
- o LPDDR3 – 240 / 120 / 80 / 60 / 48 / 40 / 34 ?
- • Operating frequency up to 1200 MHz (2400 MT/sec) data rate)
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
TSMC 28nm
Maturity
Silicon Proven
Availability
Available Now