High-performance, standard-compliant, silicon-agnostic solution designed to meet the demanding requirements of data center, hyperscaler, and AI processing environments
The 800G Ethernet Media Access Control (MAC) IP core provides a comprehensive and flexible solution for implementing the IEEE 802.3 MAC layer for high-speed Ethernet required in demanding applications such as hyperscale data centers, high-performance computing (HPC), and Artificial Intelligence (AI) / Machine Learning (ML) clusters.
Compliant with the IEEE 802.3 standard, the Comcores MAC IP ensures interoperability while offering features optimized for low latency and high throughput. The core is highly configurable and easy interfacing with Comcores IEEE 1588 Timestamping Unit (TSU) and Comcores PCS solutions.
For the client side, the IP cores use a multichannel MAC scheme to guarantee line-speed operation across Ethernet packet sizes. The scheme ensures the packet order is maintained for each MAC channel as well as cross all MAC channels. On the Client side, the core implements eight 128-bit AXI-S Client interface for 800 Gbps operation. A standard 800GMII interface is utilized towards the PHY side.
Designed for both ASIC and FPGA targets, this IP core enables seamless integration into next-generation networking equipment operating at 800 Gbps data rates.
Standards Compliance
- Full implementation of IEEE 802.3 MAC layer and reconciliation sublayer
- Compliant with Ethernet Technology Consortium 800G specification
- Support for IEEE 802.1Q VLAN and Priority Flow Control (PFC)
- IEEE 1588v2/802.3as Precision Time Protocol (PTP) support with hardware timestamping
High Performance Architecture
- Cut-through operation mode for ultra-low latency (store-and-forward optional)
- Deficit Idle Count (DIC) mechanism ensuring maximum throughput while maintaining IEEE-compliant IFG
- Full line-rate operation at 800 Gbps with 8×106.25 Gbps lanes
- Minimal latency design optimized for time-critical applications
Rich Feature Set
- 1024-bit CDMII interface to 800G PCS supporting dual 400G PCS operation
- 8 x 128-bit AXI-Stream user interface
- Hardware-assisted flow control with IEEE 802.3 PAUSE and 802.1Qbb Priority Flow Control (PFC)
- Support for jumbo frames with programmable Maximum Transmission Unit (MTU)
- Preamble/SFD generation and checking
- CRC-32 generation, checking and optional forwarding
Comprehensive Statistics and Management
- Complete set of RMON and MIB II statistics counters
- Per-frame statistics and error reporting
- IEEE managed objects for SNMP environments
- Sideband channel providing per-frame information to user applications
Flexibility and Configuration
- Configuration for multiple Ethernet rates (800G, 400G, 200G) through the same IP
- Multiple host interface options (APB, AXI4-Lite)
- Programmable MAC address filtering for unicast, multicast, and broadcast frames
- Configurable promiscuous mode
Advanced Features
- Interspersing Express Traffic (IET) support per IEEE 802.3br
- Energy Efficient Ethernet (EEE) support for reduced power consumption
- Fault signaling and handling compliant with IEEE 802.3 Clause 81
- Optional local and remote loopback modes for diagnostics
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note
- Simulation Environment, including Simple Testbed, Test case and Test Script
- Programming Register Specification
- Timing Constraints in Synopsys SDC format
- Access to support system and direct support from Comcores Engineers
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
