IP Catalog > Security IP > DPA and FIA Countermeasures IP > Common Scrambling Algorithm IP core

Common Scrambling Algorithm IP core

Overview

The Helion DVB-CSA cores implement the ETSI specified Common Scrambling Algorithm (CSA) which is used to provide the conditional access mechanism for MPEG-2 video streams for use in Pay-TV systems adopted by Digital Video Broadcasting (DVB) consortium. It has also been specified by the European Broadcasting Union (EBU) for use within Digital Satellite News Gathering (DSNG) applications, where it provides data security within the Basic Interoperable Scrambling System (BISS) Mode 1 and Mode E specifications.

Both the Scrambling and Descrambling cores have been carefully designed for optimal use in FPGA technology, and offer high throughput rates combined with low logic resource utilisation. They can support DVB scrambling and descrambling applications at data throughputs in excess of 200Mbps even in the lowest cost FPGA devices, and at rates over 500Mbps in the higher performance FPGA families – all whilst using only modest logic resources.

Key Features

  • Implements ETSI specified DVB Common Scrambling Algorithm
  • Ideal for use in BISS-E and BISS Mode-1 Digital Satellite News Gathering applications
  • Available as separate Scrambler and Descrambler cores for best system efficiency
  • Internal 3-stage pipeline for optimum Scrambler data throughput
  • Capable of Scrambler/Descrambler data throughputs in excess of 500 Mbps
  • Simple interfacing to user logic with separate key and data ports
  • Highly optimised for use in each individual FPGA technology

Block Diagram

Common Scrambling Algorithm IP core Block Diagram

Deliverables

  • Target specific netlist or fully synthesisable RTL source code
  • VHDL/Verilog simulation model and testbench
  • User documentation

Technical Specifications

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Common Scrambling Algorithm IP core
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