The DVB-CSA cores implement the ETSI specified Common Scrambling Algorithm (CSA) which is used to provide content protection and conditional access support for MPEG video streams within Digital Video Broadcasting (DVB) applications. It has been adopted for use in Pay-TV systems by the Digital Video Broadcasting (DVB) consortium.
The CSA has also been adopted by the European Broadcasting Union (EBU) for use in Digital Satellite News Gathering (DSNG) applications, where it provides data security for the Basic Interoperable Scrambling System (BISS) Mode 1 and Mode E specifications.
The Helion DVB-CSA cores are provided as separate Scrambler and Descrambler cores in order to provide the most efficient CSA solutions while providing maximum flexibility to the user.
Both cores are available in versions for use in Actel, Altera and Xilinx FPGA, and in common with all Helion IP cores they have been designed with each technology firmly in mind to yield the most efficient results. For more detailed information on these cores, please download the appropriate datasheet below.
DVB Common Scrambling Algorithm (CSA) cores
Overview
Deliverables
- Target specific netlist or fully synthesisable RTL VHDL/Verilog
- VHDL/Verilog simulation model and testbench with ETSI test vectors
- Comprehensive user documentation