Direct memory access controller with AHB interface

Overview

Direct memory access controller with AHB interface.

Speed: 133MHz AHB Clock Rate Support
Power consumption: 21.3mW power for normal case at 100MHz
Area: 37K for 0.25um Faraday cell library
Compliance to the AMBA Specification (Rev 2.0).
An AHB slave DMA interface for the DMA controller configuration, 2 AHB master interfaces for the data transfer.
A simple AHB bridge eases to configure the AHB device without needing the full-function AHB bridge.
Up to 8 configurable DMA channels.
Up to 8 configurable DMA requests.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory transfer.
Group Round Robin arbitration scheme with the 4 priority levels.
Chain Transfer support.
Hardware handshake support.
8/16/32 data width transaction support.
Big-endian and little-endian support.