Digital Clock Manager (DCM) Module
Overview
The Digital Clock Manager (DCM) primitive in Xilinx FPGA parts is used to implement delay locked loop, digital frequency synthesizer, digital phase shifter, or a digital spread spectrum. The digital clock manager module is a wrapper around the DCM primitive which allows it to be used in the EDK tool suite.
Key Features
- Wrapper around the FPGA architecture DCM primitive, providing full support for use with the EDK design tools
- Support both active high and active low reset
- Configurable BUFG insertion
Technical Specifications
Related IPs
- Mixed-Mode Clock Manager (MMCM) Module
- Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
- CRYSTALS Dilithium core for accelerating NIST FIPS 204 Module Lattice Digital Signature algorithm
- All Digital Phase Locked Loop
- Inter-Integrated Circuit (I2C) Master Module
- Serial Peripheral Interface (SPI) Master Module