The IP is compliant to the new ISO 11898-1:2015 standard, supporting both standard CAN and CAN FD. CAN FD is a new version of the CAN standard, where the payload is sent at a higher bitrate (up to 10 Mbit/s). The payload can also be up to 64 bytes long, compared to 8 bytes for normal CAN.
The IP is available for most Xilinx, Altera, Lattice and Microsemi FPGA devices, supporting native bus interfaces like AXI, Avalon and APB. Processor integration is available for SOC type of FPGAs.
The IP is designed with many features for diagnosis and CAN bus debugging, making it ideal for data loggers and similar devices. All these features can be disabled at build time, to minimize footprint for more traditional applications.
In Short
A CAN (Controller Area Network) is a multicast multimaster serial bus commonly used in automotive and industrial applications. The IP conforms to the CAN/CAN FD (Flexible Data-Rate) standard ISO 11898-1:2015 and is 100% compliant to the Bosch reference model. It supports standard CAN bus speeds between 1 kbit/s to 1Mbit/s and CAN FD data phase bit rates of up to 13.333 Mbit/s at 3 clock cycles per bit with a 40 MHz clock.
The IP may be configured to contain multiple CAN cores. These will share a receive buffer and timestamp counter, potentially saving precious resources. Data can be transferred to the host system either by reading the shared receive buffer, or using its low-latency DMA solution.
The IP is delivered as a system bus interfaceable core bundled with demo software to allow for easy integration. The bus type varies between platforms. It is also possible to directly interface the BSP (Bit Stream Processor) block. This is the core module of the IP, stripped of buffers and many features, thus making it very small. Approximate resource usage is 1,100 4-input LUTs and 330 registers.
Sample Build Sizes
The IP has been designed to have a small resource usage. Approximate build results for a few different settings are shown in the table below.
| Setup | 4-input LUTs | Registers |
| CAN core, RX buffer | 2 400 | 1 200 |
| CAN core, RX buffer with DMA | 2 500 | 1 300 |
| CAN core, RX buffer with DMA, Timestamps | 2 700 | 1 600 |
| CAN core, RX buffer with DMA, Timestamps, Bus synchronization | 2 900 | 1 800 |
