BCH code statistics for different `$mm` `$tt`
Zero latency, low gate count, low power, asynchronous BCH Code based Error Correction FEC:
The whole operation of encoding and decoding is asynchronous and is pure combinatorial gates without use of any synchronous logic, making it zero latency RTL.
Symbol Size is 1 bit and variables are ‘m’ bits wide for Galois Field operations.
BCH Error Correcting Code ECC
Overview
Key Features
- Asynchronous operation
- No clocks required.
- No storage like memories SRAMS/ROMS/FilipFlops used
- No iterative Feedback in the pipeline
- All operation is performed in 0 clock cycles.
- RTL code is generated with parameters of
- “m” the degree of primitive polynomial
- “t_max” maximum value of error symbols that can be corrected.
- corrects up to maximum number of erasure positions
- number of symbols by which the code is shortened.
- The number of error symbols (“t”) is programmable upto “t_max” .
- Separate encoders are for every “t” .
- Decoder shared for various values of “t” upto “t_max”
- Lint clean code, verified for various values of “m”, “t_max”, “t” and shortened code.
- Size of code differs for various values of “m”, “t_max” and number of symbols by which the code is shortened.
Block Diagram
Applications
- RAID
- Error Correction
- DPU for DataCenters