Advanced Encryption Standard Module

Overview

The CC-AES-AXI is a synthesisable Verilog model of a Advanced Encryption Standard module. The AES core can be efficiently implemented on FPGA and ASIC technologies.

Key Features

  • AMBA AXI4-Lite bus
  • Encryption and decryption
  • ECB mode
  • Programmable key length
  • Fully synthesizable synchronous design with positive edge clocking
  • DFT ready

Benefits

  • Synthesizable RTL Verilog source code
  • Technology independent IP Core
  • Suitable for FPGA and ASIC
  • Easy SoC integration
  • Full implementation and maintenance support with individual approach
  • Flexible licensing scheme

Block Diagram

Advanced Encryption Standard Module Block Diagram

Deliverables

  • Verilog RTL source code
  • Verification suite
  • Datasheet and integration guide
  • C-header file
  • Constraints
  • Technical support

Technical Specifications

Availability
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Semiconductor IP