065TSMC_LVDS_05 includes signal pins (INp and INn) to transmit data, and control pin EN_TX to configure the state of the transmitter. There are other two internal pins (VREF_TX and IREF_TX) to get voltage reference and current reference. PAD_OUTp and PAD_OUTn are complementary outputs to connect to the bonding pads. The block conforms to TIA/EIA-644 LVDS standards without hysteresis.
1 Gbps DDR LVDS transmitter
Overview
Key Features
- TSMC CMOS 0.065 um
- 2.5 V analog power supply
- 1.2 V digital power supply
- 1.2 V CMOS input logic signals
- 4-step (2-bit) adjustable transmitter output current range (from 1.75 mA to 7.0 mA)
- 1 Gbps (DDR MODE) switching rates
- Conforms to TIA/EIA-644 LVDS standards without hysteresis
- Temperature range: -40 °C to + 125 °C
- Optimized for pad-limited layout design
- Portable to other technologies (upon request)
Block Diagram
Applications
- Point-to-point data transmission
- Multidrop buses
- Clock distribution
- Backplane data transmission
- Cable data transmission
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentationn
Technical Specifications
Foundry, Node
TSMC CMOS 65 nm
Maturity
silicon proven
Availability
Now
TSMC
Silicon Proven:
65nm
G