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Low Bandwidth PLL IP

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Search (18)
Compare 18 Low Bandwidth PLL IP from 5 vendors (1 - 10)
  • 1.68 to 1.917 GHz Phase-Locked Loop
    • AMS SiGe BiCMOS 0.35um
    • Reference frequency from 10MHz to 125MHz
    • LO1 frequency range from 1.692GHz to 1.973GHz
    • LO2 frequency range from 175MHz to 225MHz
    Block Diagram -- 1.68 to 1.917 GHz Phase-Locked Loop
  • High Quality LC-PLLs
    • Automatically locks over an extremely wide input frequency range
    • Dual-loop P
    •  Wideband integrated jitter <400fs in integer mode, <800fs in fractional mode with high-speed / clean reference with active fractional noise cancellation
    •  Passes PCIe6 reference clock requirements with wide margin
    •  Reference spur <200fs RMS
    •  Random period jitter <30fs RMS
    • LL effective loop bandwidth can be arbitrarily small
    Block Diagram -- High Quality LC-PLLs
  • 1.013 to 1.217 GHz phase-locked loop
    • AMS SiGe BiCMOS 0.35um
    • Reference frequency from 10MHz to 125MHz
    • LO1 frequency range from 1.013GHz to 1.127GHz
    Block Diagram -- 1.013 to 1.217 GHz phase-locked loop
  • Fractional-N PLLs for Performance Computing
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLLs for Performance Computing
  • Fractional-N PLL for Performance Computing in UMC40LP
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.02 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLL for Performance Computing in UMC40LP
  • Fractional-N PLL for Performance Computing in TSMC N6/N7
    • Frequencies up to 4GHz
    • Low jitter (< 10ps RMS)
    • Small size (< 0.01 sq mm)
    Block Diagram -- Fractional-N PLL for Performance Computing in TSMC N6/N7
  • Fractional-N PLL for Performance Computing in Samsung 14LPP
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.004 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLL for Performance Computing in Samsung 14LPP
  • Fractional-N PLL for Performance Computing in Samsung 8LPP
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.003 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLL for Performance Computing in Samsung 8LPP
  • Fractional-N PLL for Performance Computing in GlobalFoundries 12LPP/14LPP
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.004 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLL for Performance Computing in GlobalFoundries 12LPP/14LPP
  • Fractional-N PLL for Performance Computing in GlobalFoundries 22FDX
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLL for Performance Computing in GlobalFoundries 22FDX
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