Integer N PLL for Frequency Synthesis
Overview
The ANLBPLL0100 is an integer-N PLL for frequency synthesis that can be used to create a low phase-noise local oscillator (LO) for applications operating in the L band (1 GHz – 2 GHz). The low phase noise results in ultra-low clock jitter for applications which require it. The frequency synthesizer consists of a clock receiver, phase-frequency detector, low-noise charge pump, active loop filter utilizing on-die and off-die components, multi-band LC VCO, and an LO output buffer. The frequency synthesizer uses a 9-bit programmable divider to support integer multiplication factors from 100 to 511.
Key Features
- 1 GHz–2 GHz LO frequency range
- 5 MHz–20 MHz input clock frequency range
- 9-bit programmable divider (100-511)
- 7-band VCO with off-chip resonator
- Programmable charge pump and loop filter
- Integrated LDO regulator
- Lock indicator
- Process: 130nm GF BiCMOS8HP
- Area = 2.74mm2 (1.48 mm x 1.85mm)
- Phase Noise: -120 dBc/Hz @ 1MHz (1.5 GHz)
- Jitter RMS: 1.2ps (12KHz-20MHz integration BW)
- Loop bandwidth: 5 KHz-50 KHz
- Lock time: 1ms
Benefits
- Low phase-noise applications
Block Diagram
Applications
- L band applications including:
- - Satellite navigation (GPS)
- - Mobile satellite telecommunications
- - Aircraft surveillance
- - Digital audio/video broadcasting
- - Astronomy
- - Amateur radio
- General purpose clock synthesis
Deliverables
- Specification
- GDS
- CDL
- LEF
- Verilog model
- .LIB
- Application documentation
Technical Specifications
Foundry, Node
GF 130nm
Maturity
Tested in Silicon
Availability
Immediate