What Is Viral in CXL 3.0?
Introduction to CXL 3.0
CXL 3.0 is an open-standard interconnect technology that builds upon PCIe 6.0 to facilitate high-speed communication between CPUs and peripheral devices. With a doubled bandwidth of 64 GT/s and enhanced fabric capabilities, CXL 3.0 aims to optimize system-level flows, improve resource utilization, and enable new device types for composable disaggregated infrastructure.
Unveiling the Viral Feature
Viral is an error containment mechanism. CXL links and CXL devices are expected to be Viral-compliant. Viral support capability and control for enabling are reflected in the DVSEC. Viral is not a replacement for existing error-reporting mechanisms. Instead, its purpose is an additional error-containment mechanism.
To read the full article, click here
Related Semiconductor IP
- CXL 3.0 Controller
- 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
- PCIe 6.0 / CXL 3.0 PHY & Controller
- CXL 3.0 Verification IP
- CXL 3.0 Integrity and Data Encryption Security Module
Related Blogs
- How CXL Is Improving Latency in High-Performance Computing
- Navigating Cache Coherence: The Back-Invalidate Feature in CXL 3.0
- Unveiling NOP Insertion Hint: A Performance Optimizer in CXL 3.0
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
Latest Blogs
- MIPI: Powering the Future of Connected Devices
- ESD Protection for an High Voltage Tolerant Driver Circuit in 4nm FinFET Technology
- Designing the AI Factories: Unlocking Innovation with Intelligent IP
- Smarter SoC Design for Agile Teams and Tight Deadlines
- Automotive Reckoning: Industry Leaders Discuss the Race to Redefine Car Development