The CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of an IP or SoC. The CXL VIP is fully compliant with latest CXL specifications. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design cycle time.
CXL 3.0 Verification IP
Overview
Benefits
- Available in native System Verilog (UVM/OVM/VMM) and Verilog.
- Unique development methodology to ensure the highest levels of quality.
- 24X5 customer support.
- Unique and customizable licensing models.
- Exhaustive set of assertions, cover points with connectivity example for all the components.
- Consistency of interface, installation, operation, and documentation across all our VIPs.
- Provide complete solution and easy integration in IP and SoC environment.
- On-the-fly protocol checking using protocol check functions, static and dynamic assertion.
- Provides a comprehensive user API (callbacks).
- Graphical analyzer for easy debugging, regression analysis, performance, statistics, charts and automatic integration.
Block Diagram
Deliverables
- CXL Host/Device
- CXL BFM/Agents for
- Host and Device sequences
- Transaction layer(CXL.IO and CXL.cache, CXL.mem)
- Link layer(CXL.IO and CXL.cache, CXL.mem)
- Arbiter/Mux layer
- PHY layer
- CXL Monitor and Scoreboard
- Test Environment & Test Suite:
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Cover Point Tests
- Compliance Tests
- Documents:
- Integration Guide
- User Manual
- Quick start Guide, Release Notes
- FAQs