The Alphawave PipeCORE PHY IP is a high-performance, low-power, PCIe 1.0 to PCIe 6.0 PHY, that is capable of also operating at 64 Gbps PAM4 PCI Express 6.0 rates (2.5/5/8/16/32/64 GT/s). It includes a hardened PMA layer and a soft PCS layer deliverable. PipeCORE is based on the industry leading AlphaCORE DSP architecture.
PipeCORE is power and performance optimized for the strenuous challenges of PCIe and is targeted to deliver unparalleled bandwidth for the next generation of computing interfaces.
Targeted for 36+ dB of channel loss for 2.5/5/8/16/32/64 GT/s PCIe and CXL rates, PipeCORE delivers a power-optimized, physical layer IP that yields more than 400 Gbps of data throughput per millimeter of silicon perimeter.
1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
Overview
Key Features
- High speed performance
- Low power, DSP based architecture provides robust operation over long copper backplanes.
- Low power architecture
- Low power DSP architectures enables next generation PCIe Gen5 and Gen6 interfaces.
- Robust training
- Integrated microcontroller per lane enables fast PCI-Express (PCIe) training in both foreground and background for both NRZ and PAM4 rates.
- Industry standard support
- The PipeCORE PCIe Gen1-5 PCS layer support both PIPE 4.X and 5.X Message Bus interfaces and has been validated with leading PCIe Controllers.
Benefits
- Receive Equalization
- Designed for closed eye, backplane systems up to 45dB of insertion loss at Nyquist for with NEXT for NRZ and 38dB for PAM4 PCIe Gen6. Digital CDR meets strict PCIe Jitter Tolerance IO Density.
- Power Optimization
- Built for high performance, PipeCORE is capable of delivering equalization for up to 45dB channels, while minimizing power consumption for NRZ and PAM4 rates.
- Configurability
- Supports 1, 4, 8, 16 lane configurations, different IP options available for north/south versus east-west orientations. PipeCORE also supports multiple rows of stacking for high density switching applications, and can also support multiple different metal options for SOC flexibility.
- Devices Used
- Standard CMOS digital devices.
Block Diagram
