How Many Cycles are Needed to Verify ARM's big.LITTLE on Palladium XP?
At the recent CDNLive! India user conference, Deepak Venkatesan and Murtaza Johar representing ARM India gave a fascinating presentation called "Verifying big.LITTLE using the Palladium XP".
ARM's big.LITTLE platform contains the combination of Cortex A15 MPCores - for high performance required in compute intensive applications - with Cortex A7 MPCores, allowing low power execution of the majority of workloads. Key to big.LITTLE is the switching between the cores, which is enabled using a Cache Coherent Interconnect - the CCI-400 fabric.
Let's first look at the results of using Palladium XP.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related Blogs
- Tips on Using e Macros to Raise Abstraction and Facilitate Reuse
- An inconvenient truth about using DDR3 SDRAM for embedded designs
- Some critical considerations for SoC and Silicon Realization teams thinking about using ARM Cortex-A7 or ARM Cortex-A8 processor cores
- The WORD on ARM's big.LITTLE Cortex-A15/A7 design philosophy from Jack Ganssle
Latest Blogs
- Evolution of CXL PBR Switch in the CXL Fabric
- CNNs and Transformers: Decoding the Titans of AI
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success