How Many Cycles are Needed to Verify ARM's big.LITTLE on Palladium XP?
October 30, 2012
At the recent CDNLive! India user conference, Deepak Venkatesan and Murtaza Johar representing ARM India gave a fascinating presentation called "Verifying big.LITTLE using the Palladium XP".
ARM's big.LITTLE platform contains the combination of Cortex A15 MPCores - for high performance required in compute intensive applications - with Cortex A7 MPCores, allowing low power execution of the majority of workloads. Key to big.LITTLE is the switching between the cores, which is enabled using a Cache Coherent Interconnect - the CCI-400 fabric.
Let's first look at the results of using Palladium XP.
To read the full article, click here
Related Semiconductor IP
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
Related Blogs
- Addressing Challenges with FPGAs in Space Using the GR716B Microcontroller
- Tips on Using e Macros to Raise Abstraction and Facilitate Reuse
- An inconvenient truth about using DDR3 SDRAM for embedded designs
- Some critical considerations for SoC and Silicon Realization teams thinking about using ARM Cortex-A7 or ARM Cortex-A8 processor cores
Latest Blogs
- How Arasan’s SoundWire PHY Can Elevate Your Next Audio SoC
- Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos
- Introducing the Akeana 1000 Series Processors
- How fast a GPU do you need for your user interface?
- PCIe 6.x and 112 Gbps Ethernet: Synopsys and TeraSignal Achieve Optical Interconnect Breakthroughs