PCIe 6.0 Address Translation Services: Verification Challenges and Strategies
Address Translation Services (ATS) is a mechanism in PCIe that allows devices to request address translations from the Input/Output Memory Management Unit (IOMMU). This is particularly important where devices need to access virtual memory. ATS enhances performance by enabling devices to cache translations, reducing the latency associated with memory access. This blog delves into the semantics of ATS request-completion protocol and Invalidation protocol. It also addresses key verification challenges that verification engineers might face while covering the error scenarios at various stages of verification.
Semantics of ATS Protocol
ATS uses a request-completion protocol between a device and a Root Complex (RC).
- The device function generates an ATS translation request that is sent upstream through the PCIe hierarchy to the RC which then forwards it to the Translation Agent (TA)
- ATS translation requests are processed for each traffic class that follows the ordering rules and issues the associated ATS translation completion
ATS uses invalidate request-completion protocol between a device and an RC and ensures that the cached address translations are not stale.
- TA (or RC) sends the invalidate request downstream to the device Address Translation Cache (ATC)
- Devices like endpoint (EP) issue one or more invalidate completion responses to TA, indicating that EP has cleared the ATC
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