TSMC Symposium: EDA/IP Ecosystem Primed for 16, 10nm Nodes
April 28, 2014
SAN JOSE, Calif. -- 28nm may still be considered the mainstream node, but for leading-edge designers, there is a clear and compelling path from there through 16nm and into even the 10nm design ecosystem.
That was the message last week from Suk Lee, Senior Director, Design Infrastructure Marketing Division, TSMC, who spoke at the annual TSMC Symposium here.
Whether it's design infrastructure (design rules, PDKs, reference flows, and so forth) or IP, TSMC has charted a course deep into the FinFET era that will take design teams well into 2020 and beyond.
Some highlights from Lee's presentation:
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