TSMC on Collaboration: JIT Ecosystem Development
Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry's Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be designed with the EDA tools already out there. Yes, new factors like signal integrity would grow in importance but this happened over several process generations and so was incremental. Basically, designers would wait for the first release of the Spice decks and the DRC rule decks and then get going.
This doesn't work any more. Since then each process generation has a major discontinuity:
- 45nm: power must be addressed
- 28nm: high-K metal gate
- 20nm: double patterning
- 16nm: FinFET
- 10nm: multiple patterning and spacer
To read the full article, click here
Related Semiconductor IP
- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
- High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
- Verification IP for DisplayPort/eDP
- Wirebond Digital and Analog Library in TSMC 65nm
Related Blogs
- TSMC Symposium: EDA/IP Ecosystem Primed for 16, 10nm Nodes
- Novatek advancing digital television with Arm POP IP on TSMC 22nm ULP
- IEDM: TSMC on 3nm Device Options
- Arm enables the lowest power IoT devices with new Ambiq Apollo4 SoC on TSMC 22nm ULP and ULL libraries
Latest Blogs
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms
- ReRAM-Powered Edge AI: A Game-Changer for Energy Efficiency, Cost, and Security