TSMC on Collaboration: JIT Ecosystem Development
Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry's Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be designed with the EDA tools already out there. Yes, new factors like signal integrity would grow in importance but this happened over several process generations and so was incremental. Basically, designers would wait for the first release of the Spice decks and the DRC rule decks and then get going.
This doesn't work any more. Since then each process generation has a major discontinuity:
- 45nm: power must be addressed
- 28nm: high-K metal gate
- 20nm: double patterning
- 16nm: FinFET
- 10nm: multiple patterning and spacer
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related Blogs
- TSMC Symposium: EDA/IP Ecosystem Primed for 16, 10nm Nodes
- Novatek advancing digital television with Arm POP IP on TSMC 22nm ULP
- IEDM: TSMC on 3nm Device Options
- Arm enables the lowest power IoT devices with new Ambiq Apollo4 SoC on TSMC 22nm ULP and ULL libraries
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview