The RISC-V Memory Consistency Model
April 24, 2017
Memory consistency models (MCMs) are known to flummox even experienced computer architects, so it is perhaps not surprising that recent news articles had some difficulty portraying the nuances behind recent findings by a team of Princeton researchers led by Professor Margaret Martonosi. The RISC-V Foundation is publishing this article to help the RISC-V community understand the deeper implications of the Princeton study.
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
Related Blogs
- Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage
- How to Reduce Memory Model Debug Time
- Memory Model Tool: Morello (and some Memory Tagging)
- High Bandwidth Memory (HBM) at the AI Crossroads: Customization or Standardization?
Latest Blogs
- Imagination Demonstrates DirectX Gaming on D-Series GPUs
- Embedded Security explained: Post-Quantum Cryptography (PQC) for embedded Systems
- Accreditation Without Compromise: Making eFPGA Assurable for Decades
- Synopsys Delivers First Complete UFS 5.0 and M‑PHY v6.0 IP Solution for Next‑Gen Storage
- World First: Synopsys MACsec IP Receives ISO/PAS 8800 Certification for Automotive and Physical AI Security