SoC Integration Mistakes
Experts at the Table, Part 2: Why making assumptions about use cases and thinking outside the box can create disasters—and where the pain really hits.
Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion.
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Blogs
- Experts At The Table: SoC Integration Mistakes
- NoC for faster SoC integration
- Bluetooth 5 IP is Ready for SoC Integration
- Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server SoC Application
Latest Blogs
- ReRAM in Automotive SoCs: When Every Nanosecond Counts
- AndeSentry – Andes’ Security Platform
- Formally verifying AVX2 rejection sampling for ML-KEM
- Integrating PQC into StrongSwan: ML-KEM integration for IPsec/IKEv2
- Breaking the Bandwidth Barrier: Enabling Celestial AI’s Photonic Fabric™ with Custom ESD IP on TSMC’s 5nm Platform