Software is from Mars, hardware is from Pluto
Engineers learn the hard way why it’s critical to communicate when a major requirement gets missed
It was the big day for the Software Team – they were scheduled to demonstrate their latest and greatest rendition of their SNMP network management software package to the Marketing Team. Months of intensive sweat-and-blood software design was about to be judged. The new hardware was… well, just hardware.
Our new prototype hardware was set up in the lab and was fully debugged, transmitting all the test traffic packets between multiport network hubs without error. This was a bit of a problem because the Software Team wanted to demonstrate how their Management Information Base (MIB) could tally and report all sorts of transmission anomalies – runt packets, CRC errored packets, collided packets, discombobulated packets – whatever. Unfortunately the Hardware Team had done its job superbly so there were no damaged packets to tally during the demonstration.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related Blogs
- Microsoft Signals the Return of "Expensive Hardware, Cheap Software"
- Business Models: EDA Is Software But It Used To Be Sold As Hardware
- IoT Changes Hardware Companies into Software Companies
- Software engineers can debug hardware too!
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?