RISC-V customization gets a standing ovation - no fragmentation drama!
Uniting diversity and compatibility
Processor vendors have always tried to create a large software ecosystem around their products, because it creates stickiness and it naturally “locks-in” large numbers of customers who have invested in the creation of dedicated software. This effect is growing over time as the quantity of software is ever increasing per product: we could talk about more than 100 million lines of code in a car!
The coupling between hardware and software comes from the selected Instruction Set Architecture (ISA) and explains why processor designers have historically strongly protected it. The ISA brings value to the processor, and so justifies higher selling prices.
Even though the RISC-V ISA is freely used and shared by multiple processor vendors, the story is not different: the value comes from the accumulation of RISC-V compatible code. However, with the ability to customize, some competitors are raising the risk of fragmentation as a weak point of the architecture. Let’s examine the facts and debunk the myths.
To read the full article, click here
Related Semiconductor IP
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
- All-In-One RISC-V NPU
- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
Related Blogs
- RISC-V customization, HW/SW co-optimization, and custom compute
- Have you checked the hidden costs of deploying an open source RISC-V core?
- The Challenges of Making Open-Source RISC-V Deployment Effective
- Codasip's Expanding RISC-V Offering