RISC-V customization gets a standing ovation - no fragmentation drama!
Uniting diversity and compatibility
Processor vendors have always tried to create a large software ecosystem around their products, because it creates stickiness and it naturally “locks-in” large numbers of customers who have invested in the creation of dedicated software. This effect is growing over time as the quantity of software is ever increasing per product: we could talk about more than 100 million lines of code in a car!
The coupling between hardware and software comes from the selected Instruction Set Architecture (ISA) and explains why processor designers have historically strongly protected it. The ISA brings value to the processor, and so justifies higher selling prices.
Even though the RISC-V ISA is freely used and shared by multiple processor vendors, the story is not different: the value comes from the accumulation of RISC-V compatible code. However, with the ability to customize, some competitors are raising the risk of fragmentation as a weak point of the architecture. Let’s examine the facts and debunk the myths.
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Related Semiconductor IP
- RISC-V CPU IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
- RISC-V High Performance Processor
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
Related Blogs
- RISC-V customization, HW/SW co-optimization, and custom compute
- What's Happening in RISC-V Land?
- Part 1: Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-V
- High-Bandwidth Core Access to Accelerators: Enabling Optimized Data Transfers with RISC-V