NVIDIA Claims TSMC 20nm will not Scale?
March 26, 2012
Interesting article from Joel Hruska on ExtremeTech: Nvidia deeply unhappy with TSMC, claims 22nm essentially worthless . The title is a bit dramatic (poetic license) but the charts are accurate to the degree that 20nm costs will be significantly higher from the start and will continue to be higher throughout production and maturity.
One reason is double patterning, which is required at 20nm (double patterning splits a design into separate masks when devices are too close together). If 28nm masks cost $3M, 20nm masks will cost $5M or more. Another reason is design complexity: layout dependent effects (LDE) and process variation will get worse at 20nm, simulation and verification requirements will explode, and the list goes on…
Related Semiconductor IP
- 112G PHY, TSMC N7 x4, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation
Related Blogs
- Samsung 20nm test chip includes ARM Cortex-M0 processor core. How many will fit on the head of a pin?
- Intel will NOT build ARM chips!
- TSMC versus Intel at 20nm!
- Apple Will NOT Manufacture SoCs at Intel
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?