Memory Standards and the Future
I sat down and talked with Amjad Qureshi recently He is vice president of research and development for the DDR PHY and controller IP. My first assumption, that he joined Cadence with the Denali acquisition, turned out to be wrong. But he does have a 25+ year long history of industry experience in IP, semiconductor, and electronics companies such as Samsung, IBM, Dell, Adaptive Chips, and Cradle Technologies. Most recently he was at ARC, which was acquired by Virage, but he left and joined Cadence before the acquisition of Virage itself. He has been at Cadence for seven years.
To read the full article, click here
Related Semiconductor IP
- DDR Controller
- DDR Controller IIP
- DDR Controller supporting DDR5 with Advanced Features Package
- DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package
- DDR Controller supporting DDR5 MRDIMM Gen2 with Advanced Features Package
Related Blogs
- Flash Forward: MRAM and RRAM Bring Embedded Memory and Applications into the Future
- The Future of PCIe Is Optical: Synopsys and OpenLight Present First PCIe 7.0 Data-Rate-Over-Optics Demo
- Navigating the Future of EDA: The Transformative Impact of AI and ML
- DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers
Latest Blogs
- How fast a GPU do you need for your user interface?
- PCIe 6.x and 112 Gbps Ethernet: Synopsys and TeraSignal Achieve Optical Interconnect Breakthroughs
- Powering the Future of RF: Falcomm and GlobalFoundries at IMS 2025
- The Coming NPU Population Collapse
- Driving the Future of High-Speed Computing with PCIe 7.0 Innovation