Memory Standards and the Future
March 31, 2016
I sat down and talked with Amjad Qureshi recently He is vice president of research and development for the DDR PHY and controller IP. My first assumption, that he joined Cadence with the Denali acquisition, turned out to be wrong. But he does have a 25+ year long history of industry experience in IP, semiconductor, and electronics companies such as Samsung, IBM, Dell, Adaptive Chips, and Cradle Technologies. Most recently he was at ARC, which was acquired by Virage, but he left and joined Cadence before the acquisition of Virage itself. He has been at Cadence for seven years.
To read the full article, click here
Related Semiconductor IP
- DDR Controller
- DDR PHY & DDR Controller IP
- DDR Controller IIP
- DDR Controller supporting DDR5 with Advanced Features Package
- DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package
Related Blogs
- Flash Forward: MRAM and RRAM Bring Embedded Memory and Applications into the Future
- Navigating the Future of EDA: The Transformative Impact of AI and ML
- DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers
- The Future of Technology: Transforming Industrial IoT with Edge AI and AR
Latest Blogs
- CNNs and Transformers: Decoding the Titans of AI
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success
- Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach