DDR PHY & DDR CONTROLLER IP

Key Features

• DDR4/DDR3/DDR2 PHY IP fully compliant with the DFI 4.0 Specification.
• LPDDR5/LPDDR4/LPDDR3/LPDDR2 PHY IP fully compliant with the DFI 4.0 Specification.
• Support speeds up to 4266Mbps.
• IP is split into 2 hard macros.
• One for commands, control and address pins and another for 8-bit data bus.
• Can support custom number of address bits.
• Compensation controller and Pads are provided for automatic driver and receiver termination impedance calibration
• Features include slew rate control, Per-bit de-skew, gate training, read and write leveling.
• JTAG signals also provided for Mentor/Synopsys and LogicVision
• Built in Self Test with a Pseudo Random Pattern Generator
• Built with Scannable flops
• Can be used in wirebond, flip-chip and cup configurations

Benefits

• Fully configurable hardened DDR4/3/2, LPDDR5/4/3/2 PHY + DDR Controller Solution
• Fully configurable for various performances and requirements, ensuring maximum performance for different system environments.
• LPDDR4: Speed up to 4266Mbps
• DFI 3.1/3.2/4.0 compliant
• Built-in self testability
• Compliance to automotive quality standard, fault coverage 99.8%
• Wide process node coverage: 40nm, 28/22nm, 16/12nm, 7nm

Block Diagram

Deliverables

• Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
• Synthesis and STA scripts
• GDSII for hard macro
• User guide documents
• SV/UVM Verification suite with BFM

Technical Specifications