DDR PHY & DDR Controller IP

Overview

Fully compliant with the DFI 4.0

Key Features

  • DDR4/DDR3/DDR2 PHY IP fully compliant with the DFI 4.0 Specification.
  • LPDDR5/LPDDR4/LPDDR3/LPDDR2 PHY IP fully compliant with the DFI 4.0 Specification.
  • Support speeds up to 4266Mbps.
  • IP is split into 2 hard macros.
  • One for commands, control and address pins and another for 8-bit data bus.
  • Can support custom number of address bits.
  • Compensation controller and Pads are provided for automatic driver and receiver termination impedance calibration
  • Features include slew rate control, Per-bit de-skew, gate training, read and write leveling.
  • JTAG signals also provided for Mentor/Synopsys and LogicVision
  • Built in Self Test with a Pseudo Random Pattern Generator
  • Built with Scannable flops
  • Can be used in wirebond, flip-chip and cup configurations

Technical Specifications

Short description
DDR PHY & DDR Controller IP
Vendor
Vendor Name
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Semiconductor IP