Industry's First LPDDR5 IP & VIP Solution Extending Leadership in DDR5/LPDDR5
Synopsys recently announced the fastest, and most power efficient DDR5 and LPDDR5 IP solutions. Industry’s first LPDDR5 controller, PHY, and verification IP solution supports data rates up to 6400 Mbps with up to 40% less area than previous generations. The LPDDR5 IP provides significant area and power savings for mobile and automotive SoCs with its dual-channel memory interface option that shares common circuitry between independent channels. The DesignWare DDR5 IP, operating at up to 4800 Mbps data rates, can interface with multiple DIMMs per channel up to 80 bits wide, delivering the fastest DDR memory interface solution for artificial intelligence (AI) and data center system-on-chips (SoCs). The DDR5 and LPDDR5 controller and PHY seamlessly interoperate via the latest DFI 5.0 interface.
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Related Semiconductor IP
- LPDDR5 Controller - Validates memory controllers for high-speed, power-efficient performance
- Simulation VIP for LPDDR5
- LPDDR5 IP solution
- LPDDR5 Synthesizable Transactor
- LPDDR5 DFI Synthesizable Transactor
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