Industry's First LPDDR5 IP & VIP Solution Extending Leadership in DDR5/LPDDR5
Synopsys recently announced the fastest, and most power efficient DDR5 and LPDDR5 IP solutions. Industry’s first LPDDR5 controller, PHY, and verification IP solution supports data rates up to 6400 Mbps with up to 40% less area than previous generations. The LPDDR5 IP provides significant area and power savings for mobile and automotive SoCs with its dual-channel memory interface option that shares common circuitry between independent channels. The DesignWare DDR5 IP, operating at up to 4800 Mbps data rates, can interface with multiple DIMMs per channel up to 80 bits wide, delivering the fastest DDR memory interface solution for artificial intelligence (AI) and data center system-on-chips (SoCs). The DDR5 and LPDDR5 controller and PHY seamlessly interoperate via the latest DFI 5.0 interface.
To read the full article, click here
Related Semiconductor IP
- LPDDR5T / LPDDR5X / LPDDR5 Controller
- LPDDR5 Controller - Validates memory controllers for high-speed, power-efficient performance
- LPDDR5 IP solution
- Simulation VIP for LPDDR5
- LPDDR5 Synthesizable Transactor
Related Blogs
- LPDDR5: Enhancements in Bandwidth, Reliability, and Power for IoT, AI, and Image Processing
- LPDDR5: Meeting Power, Performance, Bandwidth, and Reliability Requirements of AI, IoT and Automotive
- LPDDR5X - An Extension to LPDDR5 for Future Mobile System
- Synopsys TileLink Interconnect Verification IP for RISC-V SoCs
Latest Blogs
- Analog Design and Layout Migration automation in the AI era
- UWB, Digital Keys, and the Quest for Greater Range
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design
- MIPS P8700 RISC-V Processor for Advanced Functional Safety Systems
- Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces