Link Training: Establishing Link Communication Between DisplayPort Source and Sink Devices
Link training is the first stepping stone to enabling the communication channel between source and sink devices. This is where the electrical characteristics of the link along with the bitrate are fixed, and are subsequently used for the data transfers. Here the challenge for the verification engineers lies in verifying the designs for numerous combinations that are possible in the link training process.
Link training between DisplayPort source and sink devices consists of two distinct tasks that must be completed successfully and in sequence, to establish the link before frame transfers can be initiated by the source.
Related Semiconductor IP
- HOTLink II IP Core
- High Speed Data Bus (HSDB) IP Core
- 1-port Receiver or Transmitter HDCP 2.3 on HDMI 2.1 ESM
- HDMI 2.0/MHL RX Combo 1P PHY 6Gbps in TSMC 28nm HPC 1.8V, North/South Poly Orientation
- HDMI 2.0 RX PHY in SS 8LPP 1.8V, North/South Poly Orientation
Related Blogs
- Ins and outs of SS Link Training in USB3.0
- Is The ARM-Globalfoundries Link Significant?
- PCIe 5.0 Equalization Modes: Reducing Link Bring-Up Time
- HBM2E targets AI/ML training
Latest Blogs
- UALink™ Shakes up the Scale-up AI Compute Landscape
- Scaling Out Deep Learning (DL) Inference and Training: Addressing Bottlenecks with Storage, Networking with RISC-V CPUs
- Cadence Transforms Chiplet Technology with First Arm-Based System Chiplet
- Redefining XPU Memory for AI Data Centers Through Custom HBM4 – Part 2
- Redefining XPU Memory for AI Data Centers Through Custom HBM4 – Part 1