Latest Developments in Ethernet Standards
February 4, 2014
Cadence is committed to supplying Ethernet silicon and verification IP to help its customers develop Ethernet solutions. The IEEE 802.3 Ethernet standards committee recently held an interim meeting in Indian Wells, California.
I blogged about the progress being made with Ethernet standards last December. Here is an update from the January meeting:
To read the full article, click here
Related Semiconductor IP
- Verification IP for Ultra Ethernet (UEC)
- Ultra Ethernet Verification IP
- Ethernet Switch VLAN 5x100M
- 100G MAC/PCS Ultra Ethernet
- Complete 1.6T Ultra Ethernet IP Solution
Related Blogs
- Great Progress with Ethernet Standards Development
- 400G Task Force, 100G Backplane Project and Other Highlights from IEEE 802.3 Ethernet Standards Meeting
- Highlights from Recent IEEE 802.3 Ethernet Standards Meeting
- Get a Glimpse at New Ethernet Standards in the Works
Latest Blogs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
- Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production
- From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)
- Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained