Ethernet IP
Ethernet IP cores, including 112G and 224G PHYs, up to 1.6T controllers, MACsec security modules, and Verification IP, offer optimized power, performance, area, and latency for automotive, HPC, AI, and IoT SoCs.
Ethernet is defined in a number of IEEE 802.3 standards. These standards define the physical and data-link layer specifications for Ethernet.
Explore our vast directory of Ethernet IP cores below
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Ethernet IP
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Ethernet PHY IP
- Compliant to 802.3 Ethernet specification - 200GBASE-KR4, 200GBASE-CR4, 100GBASE-KR4, 100GBASE-CR4, 100GBASE-KR2, 100GBASE-CR2, 50GBASE-KR, 50GBASE-CR, 40GBASE-KR4, 40GBASE-CR4, 25GBASE-KR, 25GBASE-CR, 10GBASE-KR, 10GBASE-CR
- Data rate supported - Ethernet: NRZ 3.125 - 26.5625Gb/s, PAM4 53.125Gb/s
- DSP-based architecture using high-performance ADC/DAC for RX/TX
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1G BASE-T Ethernet Verification IP
- The 1G BASE-T Ethernet Verification IP provides deliverables an effective & efficient way to verify the components interfacing with the Ethernet interface of an IP or SoC.
- The 1G Ethernet VIP is fully compliant with the IEEE standard 802.3 specification.
- This VIP is lightweight with easy plug -and- play interface so that there is no hit on the design cycle time.
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Simulation VIP for Ethernet UEC
- Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
- Callbacks access at multiple TX and RX queue points for scoreboarding, data manipulation, and error injection
- Transaction Tracker: Configurable tracking of all the transactions on the channels
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Bridge
- A complete integrated hardware and software solution that includes a TSN-capable Ethernet switch, a DMA engine, an IEEE 802.1 AS Time Synchronization system, and a Root of Trust security module.
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Ultra Ethernet Verification IP
- The Ultra Ethernet (UE) Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet interface of an IP or SoC.
- The UE VIP is compliant with IEEE standard 802.3-2018 & UE Specifications V1.0.
- This VIP is light weight with easy plug-and-play interface so that there is no hit on the design cycle time.
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100G MAC and PCS core
- KMX 100G MAC and PCS core, which consists of media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard.
- The core implements RS FEC as defined in IEEE 802.3bj Clause 91 with independent bit error detection and bit error correction.
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40G MAC and PCS core
- KMX 40G MAC and PCS core, which including media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard.
- The core supports RS FEC as defined in Clause 74 IEEE 802.3 with independent error bit detection and error bit correction.
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Ethernet TSN MAC 40G/100G
- Silicon agnostic Ethernet TSN MAC IP with speeds of 40G and 100G, based IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features
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Verification IP for Ultra Ethernet (UEC)
- Native SystemVerilog/UVM
- Source code test suite including UNH-IOL (optional)
- Runs natively on major simulators
- Built-in protocol checks
- Verification plan and coverage
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10G/25G/40G/100Gbit/s Ethernet MAC/PCS
- 10/25/40/100 Gbit Ethernet Connectivity in Intel and AMD/Xilinx FPGA
- Designed to IEEE 802.3by specification
- Low latency, TX 11ns, RX 8ns (Modes: cut-through/store-and-forward)
- Integrated FCS(CRC32) checker and generator
