Get a Glimpse at New Ethernet Standards in the Works
I attended the IEEE 802.3 meeting in Atlanta last week. I have blogged about Ethernet standards-making meetings before and I thought I should post an update on how things have progressed. Cadence has a comprehensive design and verification IP portfolio for Ethernet, and we strive to keep it aligned to the current standards.
To read the full article, click here
Related Semiconductor IP
- MACsec Protocol Engine for 1G/10G+ Ethernet
- TSN Ethernet Endpoint Controller 10Gbps
- Multi-channel Ultra Ethernet TSS Complete Layer
- Multi-channel Ultra Ethernet TSS Transform Engine
- HPC MACsec Security Modules for Ethernet
Related Blogs
- Physical AI at the Edge: A New Chapter in Device Intelligence
- FPGA Chiplets Get a Power and Cost Makeover Thanks to New Partnership
- Want to Mix and Match Dies in a Single Package? UCIe Can Get You There
- Trust at the Core: A Deep Dive into Hardware Root of Trust (HRoT)
Latest Blogs
- A Bench-to-In-Field Telemetry Platform for Datacenter Power Management
- IDS-Verify™: From Specification to Sign-Off – Automated CSR, Hardware Software Interface and CPU-Peripheral Interface Verification
- RISC-V and GPU Synergy in Practice: A Path Towards High-Performance SoCs from SpacemiT K3
- EDA AI Agents: Intelligent Automation in Semiconductor & PCB Design
- Why Security Can't Exist Without Trust