Get a Glimpse at New Ethernet Standards in the Works
January 26, 2015
I attended the IEEE 802.3 meeting in Atlanta last week. I have blogged about Ethernet standards-making meetings before and I thought I should post an update on how things have progressed. Cadence has a comprehensive design and verification IP portfolio for Ethernet, and we strive to keep it aligned to the current standards.
To read the full article, click here
Related Semiconductor IP
- 100G MAC/PCS Ultra Ethernet
- Complete 1.6T Ultra Ethernet IP Solution
- Software solution targeting the configuration of Ethernet switches and endpoints in TSN networks
- Verification IP for Ethernet
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
Related Blogs
- Charting a Productive New Course for AI in Chip Design
- AI Is Driving a New Frontier in Chip Design
- FPGA Chiplets Get a Power and Cost Makeover Thanks to New Partnership
- Want to Mix and Match Dies in a Single Package? UCIe Can Get You There
Latest Blogs
- Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
- The Role of GPU in AI: Tech Impact & Imagination Technologies
- Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding
- Synopsys Expands Collaboration with Arm to Accelerate the Automotive Industry’s Transformation to Software-Defined Vehicles
- Deep Robotics and Arm Power the Future of Autonomous Mobility