Get a Glimpse at New Ethernet Standards in the Works
January 26, 2015
I attended the IEEE 802.3 meeting in Atlanta last week. I have blogged about Ethernet standards-making meetings before and I thought I should post an update on how things have progressed. Cadence has a comprehensive design and verification IP portfolio for Ethernet, and we strive to keep it aligned to the current standards.
To read the full article, click here
Related Semiconductor IP
- Verification IP for Ultra Ethernet (UEC)
- Ultra Ethernet Verification IP
- Ethernet Switch VLAN 5x100M
- 100G MAC/PCS Ultra Ethernet
- Complete 1.6T Ultra Ethernet IP Solution
Related Blogs
- FPGA Chiplets Get a Power and Cost Makeover Thanks to New Partnership
- Want to Mix and Match Dies in a Single Package? UCIe Can Get You There
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- Trust at the Core: A Deep Dive into Hardware Root of Trust (HRoT)
Latest Blogs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
- Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production
- From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)
- Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained