Get a Glimpse at New Ethernet Standards in the Works
I attended the IEEE 802.3 meeting in Atlanta last week. I have blogged about Ethernet standards-making meetings before and I thought I should post an update on how things have progressed. Cadence has a comprehensive design and verification IP portfolio for Ethernet, and we strive to keep it aligned to the current standards.
To read the full article, click here
Related Semiconductor IP
- 100G MAC/PCS Ultra Ethernet
- Complete 1.6T Ultra Ethernet IP Solution
- 100G Ethernet Verification IP
- Ethernet Controller
- 10M/100M/1G/2.5G Ethernet TSN End Station Controller IP
Related Blogs
- Charting a Productive New Course for AI in Chip Design
- AI Is Driving a New Frontier in Chip Design
- FPGA Chiplets Get a Power and Cost Makeover Thanks to New Partnership
- Want to Mix and Match Dies in a Single Package? UCIe Can Get You There
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power