Get a Glimpse at New Ethernet Standards in the Works
January 26, 2015
I attended the IEEE 802.3 meeting in Atlanta last week. I have blogged about Ethernet standards-making meetings before and I thought I should post an update on how things have progressed. Cadence has a comprehensive design and verification IP portfolio for Ethernet, and we strive to keep it aligned to the current standards.
To read the full article, click here
Related Semiconductor IP
- Verification IP for Ultra Ethernet (UEC)
- Ultra Ethernet Verification IP
- Ethernet Switch VLAN 5x100M
- 100G MAC/PCS Ultra Ethernet
- Complete 1.6T Ultra Ethernet IP Solution
Related Blogs
- FPGA Chiplets Get a Power and Cost Makeover Thanks to New Partnership
- Want to Mix and Match Dies in a Single Package? UCIe Can Get You There
- A look at the PowerVR graphics architecture: Tile-based rendering
- Analog Bits Builds a Road to the Future at TSMC OIP
Latest Blogs
- Shaping the Future of Semiconductor Design Through Collaboration: Synopsys Wins Multiple TSMC OIP Partner of the Year Awards
- Pushing the Boundaries of Memory: What’s New with Weebit and AI
- Root of Trust: A Security Essential for Cyber Defense
- Evolution of AMBA AXI Protocol: An Introduction to the Issue L Update
- An Introduction to AMBA CHI Chip-to-Chip (C2C) Protocol