Keeping Pace with Memory Technology using Advanced Verification
December 2, 2015
My latest webinar, Keeping Pace with Memory Technology using Advanced Verification, begins by taking the audience back in time. To a time when memories had low density, slow performance, and required expensive silicon real estate. Then I fast forward back to the future when memory technologies have evolved to support huge densities, blazing fast speeds while keeping power consumption low, and all this within very small geometry.
To read the full article, click here
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- SD4.x UHSII
Related Blogs
- Keeping Up with UCIe 1.1 Verification Using Synopsys VIP for UCIe
- Keeping up with NVMe Technology Through Compliance Testing and Pre-Production Verification
- An inconvenient truth about using DDR3 SDRAM for embedded designs
- DRAM vendors look to 40nm process technology to keep DRAM profits flowing next year
Latest Blogs
- MIPI: Powering the Future of Connected Devices
- ESD Protection for an High Voltage Tolerant Driver Circuit in 4nm FinFET Technology
- Designing the AI Factories: Unlocking Innovation with Intelligent IP
- Smarter SoC Design for Agile Teams and Tight Deadlines
- Automotive Reckoning: Industry Leaders Discuss the Race to Redefine Car Development