DRAM vendors look to 40nm process technology to keep DRAM profits flowing next year
Taiwan Economic News reports that DRAM vendors will be bringing 4x nm process technologies on line during 2010 and 2011 to keep manufacturing profits up. According to P L Pai, vice president of Nanya Technology, DRAM chip makers are presently climbing the learning curve with 40nm process technologies and he says that the lead time of 40nm immersion tools averages nine months.
Related Semiconductor IP
- Network-on-Chip (NoC)
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- DVB-S2 Demodulator
- UCIe PHY (Die-to-Die) IP
- UCIe-S 64GT/s PHY IP
Related Blogs
- Blogging from Taiwan: TSMC and 40nm Yield
- TSMC 40nm Yield Explained!
- Moore’s Law and 40nm Yield
- Anticipating the (40nm) Deluge
Latest Blogs
- Enabling End-to-End EDA Flow on Arm-Based Compute for Infrastructure Flexibility
- Real PPA improvements from analog IC migration
- Design specification: The cornerstone of an ASIC collaboration
- The importance of ADCs in low-power electrocardiography ASICs
- VESA Adaptive-Sync V2 Operation in DisplayPort VIP